Paul Lazar is a senior systems engineer specialising in system-on-chip, and integrated circuit design. He is a member of the Institute of Electrical and Electronic Engineers (IEEE), and has 7 patents issued. With a B.A.Sc in Electrical Engineering from the University of Toronto, an MBA in Business Administration, and a Master of Science Engineering (MSc) from San Jose State University, Paul is co-author of: "A 4MB On-Chip L2 Cache for a 90nm 1.6GHz 64-bit Microprocessor", IEEE Journal of Solid-State Circuits.

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